1. Field of the Invention
The present invention relates to a semiconductor device, a manufacturing method thereof and a reflection type liquid crystal display device. In particular, the present invention relates to a semiconductor device suited to directly mount other components or devices such as a liquid crystal on the surfaces of a chip, a manufacturing method thereof and a reflection type liquid crystal display device using the semiconductor device.
2. Description of Prior Art
Normally, a semiconductor device, such as an LSI, comprises chips including various types of elements formed on a semiconductor substrate made of, for example, silicon (Si) and multilayer interconnection formed on the silicon substrate to actuate the elements. The multilayer interconnection is normally formed by conducting the following steps, repeatedly, if necessary. That is, Al layers made of, for example, Al--Si alloy are formed on an interlayer insulating film such as a silicon oxide film deposited by the CVD (Chemical Vapor Deposition) method on a substrate, to thereby form metal films. Thereafter, the metal films are processed to form predetermined patterns to thereby provide interconnection. Another interlayer insulating film is further deposited on the interconnection.
Meanwhile, if driving a reflection type liquid crystal or the like mounted on the semiconductor chip such as an Si chip based liquid crystal device, it has been required to make interlayer insulating films and a passivation film serving as an uppermost insulating film, very flat and mirror-like and as thin as possible.
In the ordinary interlayer film flattening method such as an SOG (Spin On Glass) application method and an etchback method, the uneven surface of the interconnection can be flattened to such an extent to facilitate forming an upper interconnection layer thereon. However, it is impossible to provide a high-flatness, mirror-like surface. As a method of providing a highly flattened surface, there is proposed a CMP (Chemical Mechanical Polishing) method.
Description will now be given to a case where the CMP method is applied to the conventional insulating film between multilayer interconnection and the surface of the insulating film is flattened.
FIG. 20 shows an interconnection 2 formed on a flat insulating film 1 to a thickness of T1 and a flat insulating film 3 formed on the interconnection 2 to a thickness of T2. To form the insulating film 3 by using the CMP method, it is necessary to first deposit an insulating material to at least a thickness of T3 (=T1 +T2) indicated by a two-dot chain line in FIG. 20 and then to polish the deposition by a thickness (T3-T2) greater than T2. In other words, to flatten an insulating film by the CMP method, it is necessary to deposit an insulating material having a thickness of not less than twice as large as the thickness T1 of the interconnection 2 and to polish the insulating material by not less than the thickness T1.
In the meantime, according to the CMP method, polishing dispersion as high as not less than 10% of a polished amount (or thickness) might occur. It is therefore preferable to polish the deposition as little as possible for providing a flat surface.
However, if using an Al material for a interconnection layer, the thickness of the interconnection layer needs to be not less than, for example, 0.5 .mu.m so that the interconnection layer can function as an electrode or a wiring. As described above, if the interconnection 2 is formed of Al material, the polished amount or thickness is increased, and more than 0.5 .mu.m is necessary. Considering polishing dispersion, therefore, it is not favorable for the formation of a flat mirror-like surface.
Moreover, if forming a thin insulating film 3 on the interconnection 2 by the CMP method, the thickness of the film 3 tends to be uneven. This might be probably because the Al material for the interconnection as usually used is relatively soft and therefore force is exerted differently on portions where the interconnection 2 is present and portions where it is not present. From this, it is difficult to provide a completely flat surface.
As described above, according to the conventional technique, it has been quite difficult to make thin and completely flat mirror-like, interlayer insulating films and a passivation film formed above the interconnection of Al material having a thickness of not less than 0.5 .mu.m.
Furthermore, in the recent semiconductor chips, to prevent erosion of an interconnection, a silicon nitride film (to be referred to as p-SiN) deposited on an uppermost layer by a plasma CVD (Chemical Vapor Deposition) method is used as a chip protection film.
FIG. 21 shows an enlarged typical view of important parts of such a semiconductor chip. Specifically, the semiconductor chip has a structure that a first interlayer insulating film 14, a second interlayer insulating film 16 and a third interlayer insulating film 18 are formed on a semiconductor substrate 10 made of silicon (Si) and having a source and drain for the formation of a MOS transistor buried therein, through a LOCOS 12 consecutively in due order. A first interconnection layer 22 connected to a lower gate electrode 20 through a contact hole is formed on the first interlayer insulating film 14. A second interconnection layer 24 is formed on the second interlayer insulating layer 16. A bonding pad 26 made of the exposed second interconnection layer 24 is formed in the opening of the uppermost third interlayer insulating film 18. The uppermost third interlayer insulating film 18 serves as a chip protection film for the semiconductor chip.
There are some cases where other components or devices are directly mounted on a chip to provide electric connection therebetween such as Si chip based liquid crystal display device in addition to ordinary connection by bonding using the above-described bonding pad 26, depending on intended uses.
However, if other components or devices are directly mounted on a chip to provide electric connection as described above, a problem occurs that a chip protection film cannot be formed on the uppermost interconnection layer as in the case of the semiconductor chip shown in FIG. 21.